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Physical Dimensions
8.76
8.36
7.62
A
0.65
14
8
B
5.60
6.00
B
4.15
3.75
B
1.70
#1
1.27
PIN ONE
INDICATOR
(0.27)
#1
1.27
7
0.51
0.36
TOP VIEW
0.20
C B A
LAND PATTERN RECOMMENDATION
1.80 MAX
1.65
1.45
C
(R0.20)
SEE DETAIL A
0.30
0.15
B
0.05MIN
1.27
SIDE VIEW
0.10 MAX C
GAGE
END VIEW
8°
NOTES:
A) THIS DRAWING COMPLIES WITH JEDEC MS-012
EXCEPT AS NOTED.
PLANE
(R0.10)
B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-012 VALUE.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS.
E) LANDPATTERN STANDARD: SOIC127P600X145-14M
F) DRAWING FILE NAME AND REVISION : M14CREV1
0.36
SEATING
PLANE
0.90
0.50
DETAIL A
Figure 44. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 Inch Narrow Body, 225SOP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor ’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/ .
? 2009 Fairchild Semiconductor Corporation
FAN73933 ? Rev. 1.0.0
16
www.fairchildsemi.com
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